Class D amplifiers are well known to those having skill in the art. In particular, power amplifiers may be classified based on their output stages. In a class A amplifier, the output stage conducts for the entire cycle of the input signal. In contrast, the class B stage is biased at zero DC current. An intermediate stage class between A and B, referred to as class AB, biases the output stage at a non-zero DC current that is generally much smaller than the peak current of the input signal. Finally, in a class C amplifier, the output stage conducts for an interval shorter than that of the half cycle. Class A, AB and B amplifiers are widely used as output stages of operational amplifiers and audio power amplifiers. Class C amplifiers are often employed for radio frequency power amplification.
In contrast, a class D amplifier, sometimes called a "digital" amplifier, handles signals as on/off pulses using Duty-Cycle Modulation (DCM) including Pulse Duty Cycle Modulation (PDM), or Pulse Width Modulation (PWM). By using transistors as switches rather than as linear amplifiers, the class D amplifier may be highly efficient and small in size. Moreover, class D amplifiers may be capable of driving highly reactive loads with low power losses.
FIG. 1 is a simplified block diagram of a conventional class D amplifier. As shown in FIG. 1, a conventional class D amplifier 100 includes a digital or analog DCM or PWM modulator 104 that is responsive to a digital or analog input signal 102, to produce a duty cycle or width modulated square wave 114. A switching amplifier 106 is responsive to the duty cycle or width modulated square wave 114, to produce an amplified DCM/PWM square wave 116. The switching amplifier 106 may employ both positive (+) and negative (-) power supplies. A low pass filter 108 converts the amplified DCM/PWM square wave 116 into an analog output signal 112 that drives a load such as a loudspeaker 110.
Accordingly, class D amplifiers modulate the duty cycle or width of square wave pulses as a function of the input signal. When the volt-second area is identical for both the positive and negative pulses, the pulse cycle average is zero volts. This corresponds to a 50% duty cycle. By varying the duty cycle from the 50%, zero volt output state, the average output can be made positive or negative. The low pass filter 108 is used to "demodulate" the difference in duty cycle and therefore recover the modulating signal. The square wave or pulse frequency is generally set to meet the Nyquist criterion of at least twice the highest frequency to be amplified.
FIG. 2 graphically illustrates an input signal 102 and an amplified PDM square wave 116 of FIG. 1, to show the modulation of the duty cycle of a square wave as a function of the input signal 102. FIG. 3 illustrates the zero crossing of FIG. 2 in expanded form. The design and operation of the class D amplifiers are well known to those having skill in the art and need not be described further herein.
Unfortunately, despite the potential advantages of class D amplifiers noted above, practical limitations may preclude the use of class D amplifiers. In particular, in practice, a pulse frequency equal to or greater than four times the highest input signal frequency to be amplified is generally used. However, present day power devices may have limited switching speed and may therefore limit the switching frequency that can be used. This may place an upper limit on the pulse frequency, and may therefore limit the accuracy of the recovered signal.
For example, in a full bridge, four output transistors are generally used. In order to return any excess reactive energy, flyback diodes may be used. These diodes may be contained within the output transistors and/or arranged in reverse parallel with the output transistors. Two devices are arranged in series across the power supply on each side of the bridge. The load is placed midway between the output transistor nodes. The load is bridged across these nodes on each side of the bridge. Thus, the load is alternatively driven from the diagonally opposite output transistors on each side of the bridge.
Unfortunately, if the output transistors or their respective flyback diodes are still conducting current when the output stages alternate, a momentary short circuit can occur in the respective adjacent output transistor or diode, leading to common mode conduction. If not properly controlled, common mode conduction, also referred to as "shoot through", can occur in the power stages and may result in increases in power device dissipation, electromagnetic radiation, loss of efficiency and even possible destruction of the output devices.
In order to reduce the common mode conduction problem, "dead" time periods or zones between the pulses may be used. Unfortunately, the use of dead time periods may create their own problems. In particular, during the dead time, the output of the power section may not be under control. Dead time may also represent an upper limit on modulation.
Moreover, flyback diode recovery can create problems due to the slow nature of the flyback diodes. Diode recovery effects may be a major cause of power switching losses in class D amplifiers. FIGS. 4A-4D graphically illustrate an example of diode recovery in a half bridge circuit. It will be understood that in FIGS. 4A-4D, for simplification, the upper half of the bridge is driven without driving the bottom half of the bridge. FIG. 4A illustrates the current in a first output transistor (I.sub.Q1). FIG. 4B illustrates diode current in a second flyback diode (I.sub.D2). FIG. 4C illustrates the drain-to-source voltage (V.sub.DS) of a second output transistor (Q.sub.2). Finally FIG. 4D is an expansion of FIGS. 4B and 4C, to illustrate the time of greatest stress in the class D amplifier.
In addition to causing switching power losses, a considerable amount of spurious switching noise or ringing may be generated by the finite switching times of the power devices interacting with stray inductances and/or stray capacitances. This spurious noise may create additional errors in the duty cycle displacement. This switching noise is generally highly variable depending on, for example, load, supply voltages, duty cycle frequency and duty cycle. Since this noise is not predictably symmetrical and is of a high frequency nature, it may be difficult to reduce or eliminate. Damping networks placed across the outputs of the power stage can reduce spurious switching transients. However, these damping networks may themselves cause losses.
FIGS. 5A and 5B illustrate typical waveforms in a high speed switching power circuit. FIG. 5A illustrates the drain current of an output transistor and FIG. 5B illustrates the drain-to-source voltage of an output transistor. As shown, each of these waveforms includes spurious ringing. Accordingly, the use of dead time periods and the generation of spurious noise may place a limit on the accuracy of class D amplifiers, particularly at low modulation levels. This may be considered analogous to "quantization error" if the class D amplifier is regarded as a digital amplifier. Alternatively, it may be considered analogous to "crossover" or "notch" distortion in a conventional linear amplifier of class B.
One attempt at reducing or eliminating dead time in a class D amplifier is described in "Audio Amplifier Efficiency and Balanced Current Design--A New Paradigm" by McLaughlin et al, Audio Engineering Society Convention, 1997, Paper 4600 (N-5), pp. 1-6. The "Balanced Current Design" turns the opposite polarity output switches on and off simultaneously, instead of alternately. Unfortunately, it may produce asymmetry, since only one half of the diagonal bridge is active devices. Thus, the other half utilizes energy stored in the output inductors from the previous half cycle in order to complete the output waveform. Additional common mode noise may also be created, due to the special timing arrangement of the power switches. Finally, it may not offer any additional error correction capability beyond the primary duty cycle control mechanism.
Another recent attempt at overcoming the above problems is described in "Pulse Edge Delay Error Correction (PEDEC)-A Novel Power Stage Error Correction Principle for Power Digital-Analog Conversion", by Nielsen, Audio Engineering Society Convention, 1997, Paper 4602 (N-7), pp. 1-30. Pulse edge delay error correction is used to correct power stage error sources. Unfortunately, this approach may be limited in the ability to make very fine corrections.
Finally, yet another recent attempt at overcoming switching noise problems is described in Linear Technology Application Note 70 by Williams, entitled "A Monolithic Switching Regulator with 100 .mu.V Output Noise", October 1997, pp. AN701 to AN70-72. Application Note 70 discloses a low noise monolithic switching regulator referred to as the LT1 533, in which the voltage and current slew rates are independently settable by external programming resistors. Thus, as described therein, the transition time may be set at the fastest rate permitting desired noise performance using the external programming resistors.
In summary, class D amplifiers are theoretically advantageous, but may present common mode conduction and switching noise problems. Despite attempts to solve these and other problems, there continues to be a need for class D amplifiers that can reduce or eliminate these problems.